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Alif Semiconductor /AE512F80F55D5AS_CM55_HE_View /LPSPI /SPI_RXUICR

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Interpret as SPI_RXUICR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXUICR)RXUICR

Description

Receive FIFO Underflow Interrupt Clear Register

Fields

RXUICR

Clear Receive FIFO Underflow Interrupt. This bit reflects the status of the interrupt. A read from this bit clears the Receive FIFO Underflow interrupt; writing has no effect.

Links

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data